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1. general description the PTN3392 is a displayport to vga adap ter ic designed to connect a displayport source to a vga sink. the PTN3392 integrates a displayport receiver and a high-speed triple video digital-to-analog converter that supports display resolutions from vga to wuxga (see ta b l e 4 ). the PTN3392 supports either one or two displayport v1.1a lanes operating at either 2.7 gbit/s or 1.62 gbit/s per lane. the PTN3392 has ?flash-over-aux? capability enabling simple firmwa re upgradability in the field. the PTN3392 supports i 2 c-bus over aux per displayport v1.1a specification ( ref. 1 ), and bridges the vesa ddc channel to the displaypo rt interface. the PTN3392 is designed for single supply a nd minimizes application costs. it can be powered directly from the displayport source side 3.3 v supply without a need for additional core voltage regulator. the vga output is powered down when there is no valid displayport source data being transmitted. the PTN3392 also aids in monitor detection by performing load sensing and reporting sink connection status to the source. 2. features and benefits 2.1 vesa compliant displayport v1.1a converter ? main link: 1-lane and 2-lane modes supported ? hbr (high bit rate) at 2.7 gbit/s per lane ? rbr (reduced bit rate) at 1.62 gbit/s per lane ? ber (bit error rate) better than 10 ? 9 ? down-spreading ssc (spread spectrum clocking) supported ? 1 mhz aux channel ? supports native aux ch syntax ? supports i 2 c-bus over aux ch syntax ? hot plug detect (hpd) signal to the source ? cost-effective design optimized for vga application 2.2 ddc channel output ? supports 100 kbit/s i 2 c-bus speed, declared in dpcd register ? support of i 2 c-bus speed control by displayport source via dpcd registers, facilitating use of longer vga cables ? i 2 c over aux feature facilitat es full support of mccs, ddc-ci, and ddc protocols (see ref. 2 ) PTN3392 2-lane displayport to vga adapter ic rev. 01 ? 4 june 2010 product data sheet
PTN3392_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 4 june 2010 2 of 29 nxp semiconductors PTN3392 2-lane displayport to vga adapter ic 2.3 analog video output ? vsis 1.2 compliance ( ref. 3 ) for all supported video output modes ? analog rgb current-source outputs ? vsync and hsync outputs ? pixel clock up to 240 mhz ? triple 8-bit digital-to- analog converter (dac) ? direct drive of double terminated 75 load with standard 700 mv (peak-to-peak) signals 2.4 general features ? supports ?flash-over-aux? field upgradability ? monitor presence detection. connection/disconnection reported via hpd irq and dpcd update. ? all display resolutions from vga to wuxga are supported 1 , including e.g.: ? wuxga: 6 bits, 1920 1200, 60 hz, 193 mhz pixel clock rate ? wuxga: 1920 1200, 60 hz, reduced blanking, 154 mhz pixel clock rate ? uxga: 1600 1200, 60 hz, 162 mhz pixel clock rate ? sxga: 1280 1024, 60 hz, 108 mhz pixel clock rate ? xga: 1024 768, 60 hz, 65 mhz pixel clock rate ? svga: 800 600, 60 hz, 40 mhz pixel clock rate ? vga: 640 480, 60 hz, 25 mhz pixel clock rate ? any resolution and refresh rates are supported up to 8 bit color ? bits per color (bpc) supported 1 ? 6, 8 bits supported ? 10, 12, 16 bits supported by truncation to 8 msbs ? all vga colorimetry fo rmats (rgb) supported ? power modes ? active-mode power consumption: ~600 mw at uxga / 162 mhz pixel clock ~500 mw at sxga / 108 mhz pixel clock ? ~40 mw at low-power mode or before link training started ? on-board crystal oscillator for use with external 27 mhz crystal ? esd protection ? 7 kv esd hbm jedec ? 8 kv esd hbm iec 61000-4-2 ( ref. 4 ) ? 3.3 v 10 % power supply ? commercial temperature range: 0 c to 85 c ? 48-pin hvqfn, 7 mm 7mm 0.85 mm (nominal); 0.5 mm pitch; lead-free package 1. except for color depth beyond 8 bits, display resolutions and refresh rates are only limited to those which a standard 2-lane displayport configuration is able to support.
PTN3392_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 4 june 2010 3 of 29 nxp semiconductors PTN3392 2-lane displayport to vga adapter ic 3. applications ? dongle pc accessory ? dongle connected to pc displayport ou tput and connected to rgb monitor via vga cable ? PTN3392 is powered by the dp_pwr pin on the displayport connector ? desktop and notebook computers ? notebook docking stations 4. ordering information [1] PTN3392bs uses latest firmware version. [2] PTN3392bs/fx uses specific firmware version (?x? = 1, 2, 3, etc., and ch anges according to firmware version). 5. functional diagram table 1. ordering information type number topside mark package name description version PTN3392bs [1] PTN3392bs hvqfn48 plastic thermal enhanced very thin quad flat package; no leads; 48 terminals; 7 7 0.85 mm sot619-1 PTN3392bs/fx [2] PTN3392bs hvqfn48 plastic thermal enhanced very thin quad flat package; no leads; 48 terminals; 7 7 0.85 mm sot619-1 fig 1. functional diagram 002aae032 diff rcv cdr, s2p rx phy analog subsystem diff rcv cdr, s2p rcv PTN3392 drv manchester codec rx digital subsystem 10b/8b de-scram interface de-skewing 10b/8b de-scram rx phy digital aux command level module rx acli dpcd registers i 2 c-bus master flash mcu control time conv. isochronous link timing recovery main stream dac dac dac r[7:0] g[7:0] b[7:0] vga output h, v sync video dac subsystem r g b hsync vsync scl sda v bias v bias v bias monitor presence detect lane 0 lane 1 aux
PTN3392_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 4 june 2010 4 of 29 nxp semiconductors PTN3392 2-lane displayport to vga adapter ic 6. pinning information 6.1 pinning 6.2 pin description fig 2. pin configuration for hvqfn48 002aae033 PTN3392bs red scl vdd_io osc_in tdi osc_out trst_n gndd tms gndd gnd_io ldocap_core tdo vddd tck vddd vdda_dp s0 hpd s1 clk_o s2 reset_n s3 sda vsync hsync blu vdd_dac vdd_dac blu_n grn_n grn rset gnd_dac red_n gnda_dp1 ml1_n ml1_p gnda_dp0 ml0_n ml0_p rrx gnda aux_n aux_p ldocap_aux vdda 12 25 11 26 10 27 9 28 8 29 7 30 6 31 5 32 4 33 3 34 2 35 1 36 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 terminal 1 index area transparent top view table 2. pin description symbol pin type description vddd 32, 31 power digital core 3.3 v supply vdda 37 power analog aux, bias and pll 3.3 v supply voltage vdda_dp 4 power analog 3.3 v supply for displayport receiver module vdd_io 12 power i/o 3.3 v supply voltage vdd_dac 17, 18 power analog 3.3 v supply for dac gnd_io [1] 7 power i/o supply ground gnd_dac [1] 23 power analog ground for dac gnda_dp0 [1] 45 power analog ground for displayport lane0 gnda_dp1 [1] 48 power analog ground for displayport lane1 gnda [1] 41 power analog aux, bias and pll supply ground gndd [1] 28, 29 power digital core supply ground
PTN3392_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 4 june 2010 5 of 29 nxp semiconductors PTN3392 2-lane displayport to vga adapter ic displayport ml0_p 43 self-biasing differential input displayport main lane signal lane 0, positive ml0_n 44 self-biasing differential input displayport main lane signal lane 0, negative ml1_p 46 self-biasing differential input displayport main lane signal lane 1, positive ml1_n 47 self-biasing differential input displayport main lane signal lane 1, negative aux_p 39 self-biasing differential input/output displayport auxiliary channel signal, positive aux_n 40 self-biasing differential input/output displayport auxiliary channel signal, negative hpd 3 3.3 v ttl single-ended output hot-plug detect rgb dac outputs blu 16 analog output ?blue? current analog output blu_n 19 analog output ?blue? current complementary analog output grn 21 analog output ?green? current analog output grn_n 20 analog output ?green? current complementary analog output red 25 analog output ?red? current analog output red_n 24 analog output ?red? current complementary analog output rset 22 analog input/output dac full-scale current control resistor. pull down to ground by an external 1.2 k ? 1 % resistor. ddc scl 11 single-ended 5 v open-drain ddc i/o 5 v sink-side ddc clock i/o. pulled up by 1.2 k external resistor to 5 v. sda 13 single-ended 5 v open-drain ddc i/o 5 v sink-side ddc data i/o. pulled up by 1.2 k external resistor to 5 v. monitor-side sync hsync 15 single-ended 3.3 v ttl output horizontal sync signal to monitor; serial resistance of 36 is recommended. vsync 14 single-ended 3.3 v ttl output vertical sync signal to monitor; serial resistance of 36 is recommended. jtag tck 5 input jtag clock input tdo 6 output jtag data output tms 8 input jtag mode select input trst_n 9 input jtag reset (active low) input tdi 10 input jtag data input table 2. pin description ?continued symbol pin type description
PTN3392_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 4 june 2010 6 of 29 nxp semiconductors PTN3392 2-lane displayport to vga adapter ic [1] hvqfn48 package die supply ground is connected to both gnd pins and exposed c enter pad. gnd pins 7, 23, 28, 29, 41, 45, 48, and exposed center pad must be connected to supply ground for proper device operation. for enhanced thermal, electrical, and boar d level performance, the exposed pad needs to be soldered to the board using a corresponding th ermal pad on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the pcb in the thermal pad region. strap pins, s[3:0] s0 33 input open (internal pull-down) = logic 0: implement vga-side monitor detect according to vesa displayport standard v1.1a sections 7 and 8 ( ref. 1 ). refer to section 7.4.1 for s0 = 0 behavior. high (external pull-up) = logic 1: set hpd high upon vga monitor detection; set hpd low upon vga monitor detachment. refer to section 7.4.2 for s0 = 1 behavior. default s0 = 0 for standard compliance. s1 34 input reserved; leave open-circuit (default internal pull-down) s2 35 input open (internal pull-down) = logic 0 to set default i 2 c speed to 100 kbit/s. high (external pull-up) = logic 1, to set default i 2 c speed to 10 kbit/s. this pin may be left open-circuit (internal pull-down) or tied to v dd according to the desired default i 2 c speed. see more explanation in table 3 about s2 pin setting and dpcd register 00109h. s3 36 input reserved; leave open-circuit (default internal pull-down) miscellaneous reset_n 1 input hardware reset i nput (active low ); internal pull-up. a capacitor must be connected between this pin and ground. a 1 f capacitor is recommended. clk_o 2 output displayport receiver test clock output ldocap_core 30 power 1.8 v digital core supply decoupling osc_in 26 input crystal oscillator input osc_out 27 output crystal oscillator output ldocap_aux 38 power 1.8 v aux supply decoupling rrx 42 input receiver termination resistance control. a 12 k resistor must be connected between this pin and ldocap_aux (pin 38). table 2. pin description ?continued symbol pin type description
PTN3392_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 4 june 2010 7 of 29 nxp semiconductors PTN3392 2-lane displayport to vga adapter ic 7. functional description referring to figure 1 ? functional diagram ? , the PTN3392 converts the displayport ac-coupled high speed differ ential signaling protocol in to a vesa vsis 1.2 compliant analog vga signaling. the PTN3392 integrat es a displayport receiver (according to vesa displayport v1.1 a specification , ref. 1 ) and a high-speed triple 8-bit video digital-to-analog converter that supports display resolution from vga to wuxga (see table 4 ? display resolution and pixel clock rate ? ), up to a pixel clock rate of 240 mhz. the PTN3392 supports one or two displayport v1.1a main link lanes operating at either in 2.7 gbit/s or 1.62 gbit/s per lane. the ptn339 2 can drive up to 100 feet of analog video cable. the displayport receiver comprise s the following functional blocks: ? main link ? aux ch (auxiliary channel) ? dpcd (displayport configuration data) ? monitor detection ? edid handling ? video dac the rgb video data with corresponding synchron ization references is extracted from the main stream video data. main stream video at tribute information is also extracted. this information is inserted once per video frame du ring the vertical blanking period by the displayport source. the attributes describe th e main video stream format in terms of geometry, timing, and color format. the origin al clock and video stream are derived from these main link data. the PTN3392 internal dpcd registers can be accessed by the source via the auxiliary channel. the monitor?s ddc cont rol bus may also be controll ed via the auxiliary channel. a bridging conversion block tr anslates the input displayport au xiliary channel signals from the source side to the ddc signals on the sink side. the PTN3392 passes through sink-side status change (e.g., hot-plug events ) to the source side, through hpd interrupts and dpcd registers. 7.1 displayport main link the displayport main link consists of doubly terminated, ac-coupled differential pair. the 50 internally calibrated termination resistors are integrated inside PTN3392. the PTN3392 supports hbr at 2.7 gbi t/s and rbr at 1.62 gbit/s per lane. 7.2 displayport auxiliary channel the aux ch is a half-duplex, bidirectional ch annel between displayport transmitter and receiver. it consists of one differential pair transporting self-clocked data at 1 mbit/s. the PTN3392 integrates the aux ch re plier (or slave), and responds to transactions initiated by the displayport source aux ch requester (or master). the aux ch uses the manchester-ii code for th e self-clocked transmission of signals; every ?zero? is represented by low-to-high transition, and ?one? represented by high-to-low transition, in th e middle of the bit time.
PTN3392_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 4 june 2010 8 of 29 nxp semiconductors PTN3392 2-lane displayport to vga adapter ic 7.3 dpcd registers dpcd registers that are part of the vesa displayport v1.1 a are described in detail in ref. 1 . the following paragraphs only describe the specific implementation by PTN3392. the PTN3392 displayport receiv er capability and status in formation about the link are reported by displayport configuration data (d pcd) registers, when a displayport source issues a read command on the aux ch. the displ ayport source device can also write to the link configuration field of dpcd to co nfigure and initialize the link. the dpcd is displayport v1.1a compliant. it is the responsibility of th e host to only issue commands within the capability of the PTN3392 as defined in the ?r eceiver capability field? in order to prevent undefined behavior. PTN3392 specific dp cd registers are listed in table 3 . 7.3.1 PTN3392 specific dpcd register settings table 3. PTN3392 specific dpcd registers dpcd register [1] description power-on reset value read/write over aux ch receiver capability field 0000bh receive_port1_cap_1. receiverport1 capability_1. 00h read only 0000ch i 2 c-bus speed control capabilities bit map. the bit values in this register are assigned to i 2 c-bus speeds as follows: bits 7:0 0000 0001b = 1 kbit/s; supported by PTN3392 0000 0010b = 3 kbit/s; supported by PTN3392 0000 0100b = 10 kbit/s; supported by PTN3392 0000 1000b = 100 kbit/s; supported by PTN3392 0001 0000b = 400 kbit/s; not supported by PTN3392 0010 0000b = 1 mbit/s; not supported by PTN3392 0100 0000b = reserved 1000 0000b = reserved 0fh read only link configuration field 00109h i 2 c-bus speed control/status bit map. bit values in this register are assigned to i 2 c-bus speeds as follows: bits 7:0 0000 0001b = 1 kbit/s; supported by PTN3392 0000 0010b = 3 kbit/s; supported by PTN3392 0000 0100b = 10 kbit/s; supported by PTN3392 0000 1000b = 100 kbit/s; supported by PTN3392 0001 0000b = 400 kbit/s; not supported by PTN3392 0010 0000b = 1 mbit/s; not supported by PTN3392 0100 0000b = reserved 1000 0000b = reserved default value: 0000 1000b (100 kbit/s) see also behavior of pin s2 in ta b l e 2 . s2 setting read/write
PTN3392_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 4 june 2010 9 of 29 nxp semiconductors PTN3392 2-lane displayport to vga adapter ic [1] byte fields that are not explicit ly listed are by definition reserved (?res?) and their default value is 0h. automated testing su b-field (optional) 00218h to 0027fh not supported. branch device specific field 00500h branch_ieee_oui 7:0 branch vendor 24-bit ieee oui. nxp oui = 00 00h read only 00501h branch_ieee_oui 15:8 nxp oui = 60 60h read only 00502h branch_ieee_oui 23:16 nxp oui = 37 37h read only 00503h id string = 3392n2 33h read only 00504h 33h read only 00505h 39h read only 00505h 32h read only 00506h 4eh read only 00507h 32h read only 00509h hardware revision level v1.2 12h read only 0050ah, 0050bh major revision level (example: v1 .32), minor revision level (example: v1. 32 ) 01h, 20h read only 0050ch to 005ffh reserved read only table 3. PTN3392 specific dpcd registers ?continued dpcd register [1] description power-on reset value read/write over aux ch
PTN3392_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 4 june 2010 10 of 29 nxp semiconductors PTN3392 2-lane displayport to vga adapter ic 7.3.2 i 2 c over aux ch registers 7.3.2.1 i 2 c-bus speed control register (read only, 0000ch) bit or bits are set to indicate i 2 c-bus speed cont rol capabilities. displayport source reads register 0000ch and sets the i 2 c-bus speed according to the dpcd register 00109h setting. the PTN3392 then adapts its i 2 c-bus bit rate to the speed set by the displayport source. 7.3.2.2 i 2 c-bus speed control/status register (read/write, 00109h) bit values in this register are assigned to i 2 c-bus speeds. prior to software writing to this register, PTN3392 defaults to the i 2 c-bus speed (either 100 kbit/s or 10 kbit/s) selected by the s2 pin ( ta b l e 2 ). on read, the PTN3392 returns a value set to indicate the speed currently in use. on write, software provides a mask to limit the speeds to be enabled: ? the PTN3392 uses the slowest speed enabled by the mask and the PTN3392 speed capabilities. ? if the result of the mask with the speed ca pabilities is 0000 0000 b, then the PTN3392 keeps the s2 setting i 2 c-bus speed that it is using before the software write (i.e., no change). some specific examples are listed below for clarification purposes: ? if the source writes 1111 1111b, the PTN3392 uses the lowest speed of 1 kbit/s. ? if the source writes 0000 1100b, the pt n3392 uses the lower of 10 kbit/s and 100 kbit/s, i.e., 10 kbit/s. ? if the source writes 0011 0000b, the PTN3392 would stay using the same i 2 c-bus speed that it is using before the software write (i.e., no change). for ddc communication, the PTN3392 generates defer responses to the source while the i 2 c-bus transfer is taking place as specified in the displayport standard v1.1a . note that when the i 2 c-bus bit rate is set to 1 kbit/s, each bit takes 1 ms. one byte including i2c_ack takes 9 ms. given this, the displayport source should expect over 20 i2c_defer?s when requesting to read a byte over i 2 c-bus at the slowest rate.
PTN3392_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 4 june 2010 11 of 29 nxp semiconductors PTN3392 2-lane displayport to vga adapter ic 7.4 monitor detection the PTN3392 assumes 75 double termination, as shown in figure 6 . the load sensing circuit of the ptn 3392 senses a 37.5 or 75 termination respectively, when the monitor is connected or disconn ected. the load-sensing circuit is active during the vertical blanking period (never during the horizontal retrace period), so th at there will be no disturbance to the screen image ca used by the load-sensing circuit. upon detection of an rgb monitor being c onnected, the PTN3392 dynamically updates dpcd register 00200h and 00204h, to indica te the presence of a sink device being connected (see section 7.3 ). after updating the dpcd register 00200h, the PTN3392 generates an irq request on hpd. the PTN3392 implements two different ways to handle the hpd signal. the hpd behavior is governed by the s0 pin?s value after the reset and initialization sequence is completed (see figure 3 ). ? if s0 pin is tied high, hpd is only driv en high when a monitor is detected. ? if s0 is tied low, hpd is driven high irrespective of whether a vga monitor is detected. fig 3. pin s0 behavior 002aaf3 65 hpd = 0; initialize power-up hpd = 1 monitor detected? yes sink_count = 0 no s0 = low hpd = 0; initialize power-up s0 = high monitor detected? sink_count = 1 monitor detected changed? no yes generate irq_hpd pulse yes sink_count = 0 hpd = 0 no sink_count = 1 hpd = 1 monitor detected changed? no yes
PTN3392_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 4 june 2010 12 of 29 nxp semiconductors PTN3392 2-lane displayport to vga adapter ic 7.4.1 s0 = logic 0 if s0 is left open-circuit (internal pull-dow n) (displayport v1.1a compliant behavior), PTN3392 behaves as stated in vesa displayport v1.1a , sections 7 and 8. PTN3392 will keep hpd low during its internal initializat ion sequence after po wer-up. it will then update dpcd register sink_count to the ex pected value, depending if a vga monitor is detected or not, and will then assert hpd high whatever is the value of sink_count register. each time PTN3392 detects a change in the vga monitor connection status, it will update the sink_count r egister accordingly, set downstream_port_status_changed register bit to 1 and generate irq_hpd pulse to signal the source about the status change. refer to figure 3 , s0 = low flowchart. 7.4.2 s0 = logic 1 if s1 is tied to high with ex ternal pull-up (best interopera bility behavior), the PTN3392 will keep hpd low during its internal initializatio n sequence afte r power-up. it will then wait for a vga monitor to be connected downstream before asserting hpd high to force source waiting for a vga monitor before starting protocol negotiations. if a vga monitor is disconnected during normal oper ations, PTN3392 will assert hp d low so that the source will consider that no sink device is connected anymore. refer to figure 3 , s0 = high flowchart. 7.5 edid handling figure 4 shows a displayport-to-analog video converter (or dongle) situated between the displayport source and a vga monitor. the PTN3392 converts a dp i 2 c over aux request to i 2 c on the monitor's ddc bus. the monitor's edid read data is then returned to the dp source via an i 2 c over aux response issued by the PTN3392. it is the responsibility of the source to only choose video modes which are declared in the edid and to adjust the displayport link capab ilities (link rate and la ne count) to provide the necessary video bandwidth. the PTN3392 does not cache or modify the edid to match the capabilities of the displayport link data. if the displayport source drives display modes that are not specified in the edid mode list, the PTN3392 will not detect such conditions, and will display at its output what it is presented by the displayport source. fig 4. displayport to vga adapter ic (dongle) sits between the displayport source and a vga monitor with edid dp tx 002aae0 39 box-to-box displayport source device dp rx with dpcd video dac displayport to vga adapter ic box-to-box legacy vga display with edid sink device
PTN3392_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 4 june 2010 13 of 29 nxp semiconductors PTN3392 2-lane displayport to vga adapter ic 7.6 triple 8-bit video dacs and vga outputs the triple 8-bit video dacs output a 700 m v (peak-to-peak) analog video output signal into 37.5 load, as is the case of a doubly terminated 75 cable. the dac is capable of supporting the maximum pixel rate supported by a two-lane dp link (240 mhz). the PTN3392 generates the rgb video timing and synchronization signals, rgb signals are then sent to the dacs for conversion to analog signals. 7.6.1 dac reference resistor an external reference resistor must be conne cted between pin rset and analog ground. this resistor sets the reference current whic h determines the analog output level, and is specified as 1.2 k with a 1 % tolerance. this value a llows a 0.7 v (peak-to-peak) output into a 37.5 load, such as a double-terminated 75 coaxial cable. 8. power-up and reset PTN3392 has built-in power-on reset circuitry which automatically sequences the part through reset and initialization. for proper behavior, a capacitor should be connected fr om the reset_n pi n to ground to slow down the internal reset pulse; 1 f capacitance is recommended. before link is established, the PTN3392 holds vsync an d hsync signals high and blanks the rgb signals. while the PTN3392 performs initialization, ? the hpd signal is driven low, to indica te to the displayport source that the PTN3392 is not ready for link communication ? the red, grn, blu and complementary outputs (red_n, g rn_n, blu_n) are disabled ? the vsync and hsync outputs are driven high
xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x PTN3392_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 4 june 2010 14 of 29 nxp semiconductors PTN3392 2-lane displayport to vga adapter ic 9. application de sign-in information (1) 1 f is recommended. (2) example of external dc/dc regulator. fig 5. application diagram 002aae2 52 37 38 39 40 41 42 43 44 45 46 47 48 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 PTN3392 1.2 k 1 % red_n gnd_dac rset grn grn_n blu_n vdd_dac vdd_dac blu hsync vsync sda s3 s2 s1 s0 vddd vddd gndd gndd osc_out osc_in red vdda ldocap_aux aux_p aux_n gnda rrx ml0_p ml0_n gnda_dp ml1_p ml1_n gnda_dp v dd(3v3)aux 27 mhz 12 12 21 21 0.1 f 0.1 f 12 0.1 f 12 0.1 f reset_n clk_o hpd vdda_dp tck tdo gnd_io tms trst_n tdi scl vdd_io 100 k 1 2 3 4 5 6 7 8 9 10 11 12 lane0p gnd lane0n lane1p gnd lane1n lane2p gnd lane2n lane3p gnd lane3n 13 14 15 16 17 18 19 20 gnd_down1 gnd_down2 auxp gnd auxn hpd rtn dp_pwr j1 1 m 1 m 1 m 1 m v dd(3v3) 12 0.1 f v dd(3v3) 21 10 f 6.3 v 1.2 k 1.2 k v dd(5v) sda grn blue_rtn hs blue vdd(5v) vs n.c. gnd scl gnd red_rtn n.c. red grn_rtn 6 11 1 7 12 2 8 13 3 9 14 4 10 15 5 vga connector vdd_conn_5v v dd(3v3) 12 2.2 f in 5 shdn 3 gnd 2 out 1 6 4 cneg cpos dc/dc 21 0.22 f 12 2.2 f v dd(5v) vdd_conn_5v (2) 21 10 f 6.3 v 2 1 21 22 23 24 gnd_c gnd_c gnd_c gnd_c dp conn 12 1 f 12 0.1 f v dd(3v3)aux v dd(3v3) (1) v dd(3v3) 20 pf 20 pf ldocap_core v dd(3v3) 12 k 47 nh 3.3 pf 75 47 nh 3.3 pf 75 47 nh 3.3 pf 75 10 pf 10 pf 2.2 f 2.2 f 0.1 f v dd(3v3) 0.1 f 36 36 47 at 100 mhz 47 at 100 mhz 47 at 100 mhz
PTN3392_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 4 june 2010 15 of 29 nxp semiconductors PTN3392 2-lane displayport to vga adapter ic 9.1 display resolution ta b l e 4 lists some example display resolutions and clock rates that PTN3392 supports. (refer to footnote 1 on page 2 .) the available bandwidth over a 2-lane hbr dis playport v1.1a link limits pixel clock rate support to: ? 240 mhz at 6 bpc ? 180 mhz at 8 bpc 9.2 power supply filter all supply pins can be tied to a single 3.3 v power source. sufficient decoupling capacitance to ground should be connected from each v cc pin directly to ground to filter supply noise. (refer to figure 5 ? application diagram ? .) 9.3 dac terminations we recommend the dac outputs to use 75 double termination. figure 6 shows an example of vga dongle application. a 75 termination is used to terminate inside the dongle, and another 75 termination is typically used in side the rgb monitor. the load sensing mechanism assumes this double termination. table 4. display resolution and pixel clock rate display type active video total frame bits per pixel frame rate (hz) pixel clock (mhz) data rate (gbit/s) horizontal vertical horizontal vertical vga 640 480 800 525 24 59.94 25.175 0.8 svga 800 600 1056 628 24 60.32 40.002 1.2 xga 1024 768 1344 806 24 60 64.996 1.9 sxga 1280 1024 1688 1066 24 60.02 108.000 3.2 sxga 1280 1024 1728 1072 24 85 157.5 4.7 uxga 1600 1200 2160 1250 24 60 162.000 4.9 qxga 2048 1536 2144 1555 24 49.266 164.249 4.9 wuxga 1920 1200 2080 1235 24 59.95 153.883 4.6 wuxga 1920 1200 2592 1245 18 59.885 193.25 4.35 fig 6. recommended dac terminations for PTN3392 002aae04 4 dac red, grn, blu red_n, grn_n, blu_n dongle pcb emi filter 75 75 vga cable double-ended termination monitor 75
PTN3392_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 4 june 2010 16 of 29 nxp semiconductors PTN3392 2-lane displayport to vga adapter ic 10. limiting values [1] human body model: ansi/eos/esd-s5.1-1994, standard for esd sensitivity testing, human body model - component level; electrostatic disc harge association, rome, ny, usa. [2] charged device model: ansi/eos/esd-s5.3-1-1999, standard for esd sensitivity testing, charged device model - component level ; electrostatic disc harge association, rome, ny, usa [3] iec 61000-4-2, level 4 ( ref. 4 ). 11. recommended operating conditions [1] input signals to these pins must be ac-coupled. table 5. limiting values in accordance with the absolute ma ximum rating system (iec 60134). symbol parameter conditions min max unit v dda analog supply voltage ? 0.3 +3.8 v v ddd digital supply voltage ? 0.3 +4.6 v v i input voltage 3.3 v cmos inputs ? 0.3 v dd +0.5 v t stg storage temperature ? 65 +150 c v esd electrostatic discharge voltage hbm [1] - 7000 v cdm [2] - 1000 v iec contact discharge to signal pins (to gnd) [3] - 8000 v table 6. operating conditions symbol parameter conditions min typ max unit v dda analog supply voltage 3.0 3.3 3.6 v v ddd digital supply voltage 3.0 3.3 3.6 v v i input voltage 3.3 v cmos inputs 0 3.3 3.6 v sda and scl inputs with respect to ground 05 5.5v v i(av) average input voltage dc value at ml_lane0+, ml_lane0 ? , ml_lane1+, ml_lane1 ? , aux_ch+, aux_ch ? inputs [1] -0 - v r ext(rset) external resistance on pin rset between rset (pin 22) and gnd - 1.2 1% - k t amb ambient temperature commercial grade 0 - 85 c
PTN3392_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 4 june 2010 17 of 29 nxp semiconductors PTN3392 2-lane displayport to vga adapter ic 12. characteristics 12.1 current consumption, power dissipation and thermal characteristics 12.2 displayport receiver main link [1] range is nominal 350 ppm. displayport link rx does not require local crystal for link clock generation. [2] up to 0.5 % down spread is supported. modulation frequency range of 30 khz to 33 khz must be supported. table 7. current consumption, power dissipation and thermal characteristics symbol parameter conditions min typ max unit i dd supply current normal operation, uxga / 162 mhz pixel clock -180-ma i dd(stb) standby supply current standby mode - 12 - ma p power dissipation normal operation, uxga / 162 mhz pixel clock -600-mw r th(j-a) thermal resistance from junction to ambient in free air for sot619-1 - 35 - k/w r pu pull-up resistance reset_n pin; 0 v v i v dd 44 66 95 k r pd pull-down resistance s0 to s3 pins; 0 v v i v dd 44 66 95 k table 8. displayport receiver main link characteristics symbol parameter conditions min typ max unit ui unit interval for high bit rate (2.7 gbit/s per lane) [1] - 370 - ps for low bit rate (1.62 gbit/s per lane) [1] - 617 - ps f down_spread link clock down spreading [2] 0.0- 0.5% v rx_diffp-p differential input peak-to-peak voltage at rx package pins for high bit rate [3] 120 - - mv for reduced bit rate [3] 40 - - mv t rx_eye_conn receiver eye time at rx-side connector pins for high bit rate [4] 0.51 - - ui for reduced bit rate [4] [5] 0.25 - - ui t rx_eye_chip receiver eye time at rx package pins for high bit rate [4] 0.47 - - ui for reduced bit rate [4] [5] 0.22 - - ui t rx_eye_m-mjt_chp time between jitter median and maximum deviation (package pins) for high bit rate [4] - - 0.265 ui for reduced bit rate [4] [5] - - 0.39 ui v rx_dc_cm rx dc common mode voltage [6] 0- 2.0v i rx_short rx short-circuit current limit [7] --50ma l rx_skew total skew inter-pair; lane-to-lane skew at rx package pins [8] - - 5200 ps lane intra-pair skew at rx package pins; for high bit rate [9] - - 100 ps for reduced bit rate [9] - - 300 ps f rx_tracking_bw jitter tracking bandwidth [10] 20 - - mhz
PTN3392_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 4 june 2010 18 of 29 nxp semiconductors PTN3392 2-lane displayport to vga adapter ic [3] informative; refer to figure 7 for definition of differential voltage. [4] t rx_eye_m-mjt_chp specifies the total allowable deterministic jitter (dj). [5] 1 ? t rx_eye_conn specifies the allowable total jitter (tj). [6] common mode voltage is equal to v bias_rx voltage. [7] total drive current of the input bias circuit when it is shorted to its ground. [8] maximum skew limit between differ ent rx lanes of a displayport link. [9] maximum skew limit between d+ and d ? of the same lane. [10] minimum cdr tracking bandwidth at the receiver when the input is repetition of d10.2 symbols without scrambling. 12.3 displayport receiver aux ch [1] results in the bit rate of 1 mbit/s including the overhead of manchester ii coding. [2] each pulse is a ?0 ? in manchester ii code. [3] period after the aux ch stop condition for which the bus is parked. [4] maximum allowable ui variation within a single transaction at connector pins of a transmitting device. equal to 24 ns maximum . the transmitting device is a source devi ce for a request transaction and a si nk device for a reply transaction. [5] maximum allowable ui variation within a single transaction at connector pins of a receiving devi ce. equal to 30 ns maximum. t he transmitting device is a source devi ce for a request transaction and a si nk device for a reply transaction. pre-emphasis = 20log(v diff_pre /v diff ) fig 7. definitions of pre-emphasis and differential voltage 002aaf3 63 v d+ v cm v d ? v diff_pre v diff table 9. displayport receive r aux ch characteristics symbol parameter conditions min typ max unit ui unit interval aux [1] 0.4 0.5 0.6 s n precharge_pulses number of precharge pulses [2] 10 - 16 t aux_bus_park aux ch bus park time [3] 10 - - ns t jit(cc) cycle-to-cycle jitter time transmitting device [4] - - 0.04 ui receiving device [5] - - 0.05 ui v aux_diffp-p aux differential peak-to-peak voltage transmitting device [6] 0.39 - 1.38 v receiving device [6] 0.32 - 1.36 v r aux_term(dc) aux ch termination dc resistance informative - 100 - v aux_dc_cm aux dc common-mode voltage [7] 0- 2.0v v aux_turn_cm aux turnaround common-mode voltage [8] --0.4v i aux_short aux short-circuit current limit [9] --90ma c aux aux ac coupling capacitor [10] 75 - 200 nf
PTN3392_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 4 june 2010 19 of 29 nxp semiconductors PTN3392 2-lane displayport to vga adapter ic [6] v aux_diffp-p = 2 | v aux+ ? v aux ? | . [7] common-mode voltage is equal to v bias_tx (or v bias_rx ) voltage. [8] steady-state common-mode voltage shift between transmit and receive modes of operation. [9] total drive current of the transmitter when it is shorted to its ground. [10] the aux ch ac coupling capacitor placed both on the displayport sour ce and sink devices. 12.4 hpd characteristics 12.5 ddc characteristics [1] v cc is the pull-up voltage for ddc. table 10. hpd characteristics symbol parameter conditions min typ max unit output characteristics v oh high-level output voltage i oh =2ma 2--v v ol low-level output voltage i ol = ? 2ma - - 0.8 v i osh high-level short-circuit output current drive high; cell connected to ground --129ma i osl low-level short-circuit output current drive low; cell connected to v dd --126ma table 11. ddc characteristics v cc = 4.5 v to 5.5 v. [1] symbol parameter conditions min typ max unit input characteristics v ih high-level input voltage 2 - 5.5 v v il low-level input voltage ? 0.5 - +0.8 v v i(hys) hysteresis of input voltage 0.1 v dd -- v i li input leakage current v i =5.5v - - 1 a output characteristics i ol low-level output current v ol =0.4v 3.0 - - ma i o(sc) short-circuit output current drive low; cell connected to v dd --40.0ma c io input/output capacitance v i = 3 v or 0 v; v dd =3.3v - 6 7 pf v i = 3 v or 0 v; v dd =0v - 6 7 pf
PTN3392_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 4 june 2010 20 of 29 nxp semiconductors PTN3392 2-lane displayport to vga adapter ic 12.6 dac 12.7 hsync, vsync characteristics [1] the parameter values specified are simulated and absolute values. 12.8 strap pins s[3:0] table 12. dac characteristics symbol parameter conditions min typ max unit n res(dac) dac resolution - - 8 bit f clk clock frequency - - 240 mhz i o(dac) dac output current vari ation dac-to-dac - - 4 % inl integral non-linearity ? 1 0.5 +1 lsb dnl differential non-linearity ? 1- +1lsb v o(dac) dac output voltage 0 - 1.25 v c o(dac) dac output capacitance - 3.5 - pf ct(dac) dac crosstalk between dac outputs - ? 54 - db table 13. hsync and vsync characteristics symbol parameter conditions min typ max unit output characteristics v oh high-level output voltage i oh =8ma 2 - - v v ol low-level output voltage i ol = ? 8ma - - 0.8 v i osh high-level short-circuit output curr ent drive high; cell connected to ground [1] - - 129.0 ma i osl low-level short-circuit output current drive low; cell connected to v dd [1] - - 126.0 ma table 14. strap pins s[3:0] characteristics symbol parameter conditions min typ max unit input characteristics v ih high-level input voltage 0.7 v dd -- v v il low-level input voltage 0.3 v dd v weak pull-down characteristics i pd pull-down current v i =v dd 25.0 50.0 95.0 a
PTN3392_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 4 june 2010 21 of 29 nxp semiconductors PTN3392 2-lane displayport to vga adapter ic 12.9 jtag and reset_n table 15. jtag and reset_n characteristics symbol parameter conditions min typ max unit input characteristics v ih high-level input voltage 0.7 v dd -- v v il low-level input voltage 0.3 v dd v output characteristics v oh high-level output voltage reset_n; i oh =4ma 2 - - v jtag; i oh =2ma 2 - - v v ol low-level output voltage reset_n; i ol = ? 4ma - - 0.8 v jtag; i ol = ? 2ma - - 0.8 v
PTN3392_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 4 june 2010 22 of 29 nxp semiconductors PTN3392 2-lane displayport to vga adapter ic 13. package outline fig 8. package outline sot619-1 (hvqfn48) 0.5 1 a 1 e h b unit y e 0.2 c references outline version european projection issue date iec jedec jeita mm 7.1 6.9 d h 5.25 4.95 y 1 7.1 6.9 5.25 4.95 e 1 5.5 e 2 5.5 0.30 0.18 0.05 0.00 0.05 0.1 dimensions (mm are the original dimensions) sot619-1 mo-220 - - - - - - 0.5 0.3 l 0.1 v 0.05 w 0 2.5 5 mm scale sot619 -1 hvqfn48: plastic thermal enhanced very thin quad flat package; no leads; 4 8 terminals; body 7 x 7 x 0.85 mm a (1) max. a a 1 c detail x y y 1 c e l e h d h e e 1 b 13 24 48 37 36 25 12 1 x d e c b a e 2 01-08-08 02-10-18 terminal 1 index area terminal 1 index area 1/2 e 1/2 e a c c b v m w m e (1) note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included. d (1)
PTN3392_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 4 june 2010 23 of 29 nxp semiconductors PTN3392 2-lane displayport to vga adapter ic 14. soldering of smd packages this text provides a very brief insight into a complex technology. a more in-depth account of soldering ics can be found in application note an10365 ?surface mount reflow soldering description? . 14.1 introduction to soldering soldering is one of the most common methods through which packages are attached to printed circuit boards (pcbs), to form electr ical circuits. the soldered joint provides both the mechanical and the electrical connection. th ere is no single sold ering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount devices (smds) are mixed on one printed wiring board; however, it is not suitable for fine pitch smds. reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 14.2 wave and reflow soldering wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. the wave soldering process is suitable for the following: ? through-hole components ? leaded or leadless smds, which are glued to the surface of the printed circuit board not all smds can be wave soldered. packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. also, leaded smds with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased pr obability of bridging. the reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. leaded packages, packages with solder balls, and leadless packages are all reflow solderable. key characteristics in both wave and reflow soldering are: ? board specifications, in cluding the board finish , solder masks and vias ? package footprints, including solder thieves and orientation ? the moisture sensitivit y level of the packages ? package placement ? inspection and repair ? lead-free soldering versus snpb soldering 14.3 wave soldering key characteristics in wave soldering are: ? process issues, such as application of adhe sive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave ? solder bath specifications, including temperature and impurities
PTN3392_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 4 june 2010 24 of 29 nxp semiconductors PTN3392 2-lane displayport to vga adapter ic 14.4 reflow soldering key characteristics in reflow soldering are: ? lead-free versus snpb solderi ng; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see figure 9 ) than a snpb process, thus reducing the process window ? solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board ? reflow temperature profile; this profile includ es preheat, reflow (in which the board is heated to the peak temperature) and coolin g down. it is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). in addition, the peak temperature must be low enough that the packages and/or boards are not damaged. the peak temperature of the package depends on package thickness and volume and is classified in accordance with ta b l e 1 6 and 17 moisture sensitivity precautions, as indicat ed on the packing, must be respected at all times. studies have shown that small packages reach higher temperatures during reflow soldering, see figure 9 . table 16. snpb eutectic process (from j-std-020c) package thickness (mm) package reflow temperature ( c) volume (mm 3 ) < 350 350 < 2.5 235 220 2.5 220 220 table 17. lead-free process (from j-std-020c) package thickness (mm) package reflow temperature ( c) volume (mm 3 ) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245
PTN3392_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 4 june 2010 25 of 29 nxp semiconductors PTN3392 2-lane displayport to vga adapter ic for further information on temperature profiles, refer to application note an10365 ?surface mount reflow soldering description? . 15. abbreviations msl: moisture sensitivity level fig 9. temperature profiles for large and small components 001aac844 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = msl limit, damage level peak temperature table 18. abbreviations acronym description aux ch auxiliary channel ber bit error rate bpc bits per color cdm charged-device model cmos complementary metal-oxide semiconductor dac digital-to-analog converter ddc data display channel dj deterministic jitter dp displayport (vesa) dpcd displayport configuration data ecc error correction code edid extended display identification data esd electrostatic discharge hbm human body model hbr high bit rate hdcp high-bandwidth digital content protection hpd hot plug detect i 2 c-bus inter-integrated circuit bus iec international electrotechnical commission
PTN3392_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 4 june 2010 26 of 29 nxp semiconductors PTN3392 2-lane displayport to vga adapter ic 16. references [1] vesa displayport standard ? version 1, revision 1a; january 11, 2008 [2] display data channel command interface standard ? version 1.1; october 29, 2004 [3] video signal standard (vsis) ? version 1, rev. 2; december 12, 2002 [4] iec 61000-4-2, electromagnetic comp atibility (emc) - part 4-2: testing and measurement techniques ? electrostatic discharge (esd) immunity test, edition 2.0, 2008-12 17. revision history i/o input/output lsb least significant bit mccs monitor control command set (vesa) msb most significant bit qxga quad extended graphics array rbr reduced bit rate rgb red/green/blue ssc spread spectrum clocking svga super video graphics array sxga super extended graphics array tj total jitter ui unit interval uxga ultra extended graphics array vesa video electronics standards association vga video graphics array vsis video signal interface standard wuxga wide ultra extended graphics array xga extended graphics array table 18. abbreviations ?continued acronym description table 19. revision history document id release date data sheet status change notice supersedes PTN3392_1 20100604 product data sheet - -
PTN3392_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 4 june 2010 27 of 29 nxp semiconductors PTN3392 2-lane displayport to vga adapter ic 18. legal information 18.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 18.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? 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stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. export control ? this document as well as the item(s) described herein may be subject to export control regulations. export might require a prior authorization from national authorities. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this docu ment contains the product specification.
PTN3392_1 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. product data sheet rev. 01 ? 4 june 2010 28 of 29 nxp semiconductors PTN3392 2-lane displayport to vga adapter ic non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive s pecifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully indemnifies nxp semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive app lications beyond nxp semiconductors? standard warranty and nxp semiconduct ors? product specifications. 18.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. 19. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
nxp semiconductors PTN3392 2-lane displayport to vga adapter ic ? nxp b.v. 2010. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 4 june 2010 document identifier: PTN3392_1 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 20. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 2.1 vesa compliant displayport v1.1a converter. . 1 2.2 ddc channel output . . . . . . . . . . . . . . . . . . . . . 1 2.3 analog video output . . . . . . . . . . . . . . . . . . . . . 2 2.4 general features . . . . . . . . . . . . . . . . . . . . . . . . 2 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 ordering information . . . . . . . . . . . . . . . . . . . . . 3 5 functional diagram . . . . . . . . . . . . . . . . . . . . . . 3 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 4 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 functional description . . . . . . . . . . . . . . . . . . . 7 7.1 displayport main link . . . . . . . . . . . . . . . . . . . . 7 7.2 displayport auxiliary channel . . . . . . . . . . . . . . 7 7.3 dpcd registers. . . . . . . . . . . . . . . . . . . . . . . . . 8 7.3.1 PTN3392 specific dpcd re gister settings . . . . 8 7.3.2 i 2 c over aux ch registers . . . . . . . . . . . . . . . 10 7.3.2.1 i 2 c-bus speed control register (read only, 0000ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 7.3.2.2 i 2 c-bus speed control/status register (read/write, 00109h) . . . . . . . . . . . . . . . . . . . . 10 7.4 monitor detection . . . . . . . . . . . . . . . . . . . . . . 11 7.4.1 s0 = logic 0. . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7.4.2 s0 = logic 1. . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7.5 edid handling . . . . . . . . . . . . . . . . . . . . . . . . 12 7.6 triple 8-bit video dacs and vga outputs . . . 13 7.6.1 dac reference resistor . . . . . . . . . . . . . . . . . . 13 8 power-up and reset . . . . . . . . . . . . . . . . . . . . . 13 9 application design-in information . . . . . . . . . 14 9.1 display resolution . . . . . . . . . . . . . . . . . . . . . . 15 9.2 power supply filter . . . . . . . . . . . . . . . . . . . . . 15 9.3 dac terminations . . . . . . . . . . . . . . . . . . . . . . 15 10 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 16 11 recommended operating conditions. . . . . . . 16 12 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 17 12.1 current consumption, power dissipation and thermal characteristics . . . . . . . . . . . . . . . . . . 17 12.2 displayport receiver main link . . . . . . . . . . . . 17 12.3 displayport receiver aux ch . . . . . . . . . . . . . 18 12.4 hpd characteristics . . . . . . . . . . . . . . . . . . . . 19 12.5 ddc characteristics . . . . . . . . . . . . . . . . . . . . 19 12.6 dac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 12.7 hsync, vsync characteristics. . . . . . . . . . . 20 12.8 strap pins s[3:0] . . . . . . . . . . . . . . . . . . . . . . . 20 12.9 jtag and reset_n . . . . . . . . . . . . . . . . . . . 21 13 package outline. . . . . . . . . . . . . . . . . . . . . . . . 22 14 soldering of smd packages . . . . . . . . . . . . . . 23 14.1 introduction to soldering. . . . . . . . . . . . . . . . . 23 14.2 wave and reflow soldering. . . . . . . . . . . . . . . 23 14.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . 23 14.4 reflow soldering . . . . . . . . . . . . . . . . . . . . . . 24 15 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 25 16 references. . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 17 revision history . . . . . . . . . . . . . . . . . . . . . . . 26 18 legal information . . . . . . . . . . . . . . . . . . . . . . 27 18.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 27 18.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 18.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 27 18.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 28 19 contact information . . . . . . . . . . . . . . . . . . . . 28 20 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

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